1. Field
This disclosure relates generally to non-volatile memories (NVMs), and more specifically, to patterning gate stacks of the NVMs.
2. Related Art
Gate stacks of NVM bitcells often include two layers of conductive material and one of those conductive layers is also used for forming logic circuits or other circuits. One of the objectives is to not use any more mask steps than necessary; the fewer the better. Another consideration is that etches vary in their selectivity and that for the gate stack in particular it is desirable to have nearly vertical sidewalls. The etchants with the best selectivity may not be the best for obtaining vertical sidewalls. For some etches end point detection is very important. This can arise because of selectivity issues so that an over etch is a limited option. Further, an over etch can result in undesirable polymers being left behind.
FIGS. 30-32 illustrate cross-sectional views of various stages during the formation of an integrated circuit having an NVM region and a tile region, in accordance with the prior art. Referring to FIG. 1, a first polysilicon layer is formed over the substrate in both the NVM region and the tile region. The first polysilicon layer is patterned such that a portion remains between the isolation regions in each of the NVM and tile regions. Subsequently, a dielectric layer is formed over the first polysilicon layer in both the NVM and tile regions, and a second polysilicon layer is formed over the dielectric layer in both the NVM and tile regions. In FIG. 2, a photoresist layer is formed over the second polysilicon layer and patterned, wherein the remaining portions of the photoresist layer correspond to a gate stack in the NVM region and a tile feature in the tile region. Each of the first polysilicon layer, dielectric layer, and the second dielectric layer is simultaneously etched, using the patterned photoresist layer, in the NVM region and the tile region. Therefore, referring to FIG. 3, the simultaneous etching in the NVM region and the tile region result in the formation of a gate stack in the NVM region having a portion of the first polysilicon layer and the second polysilicon layer and a tile feature in the tile region having both a portion of the first polysilicon layer and the second polysilicon layer. The tile feature in the tile region is formed over the substrate, between the isolation regions and not on the isolation regions. The simultaneous etching of the tile feature in the tile region at the same time as the gate stack in the NVM region provides additional material for use in end point detection during the gate stack etch. Note that the resulting tile feature is not electrically active. Accordingly, it is desirable to provide the patterning of a gate stack of an NVM that takes into account the above issues to result in improved patterning.